Recently, performances of semiconductor memories (for example, DRAM: Dynamic Random Access Memory), processors, and the like used for computers and other information processing devices are significantly improving. Accordingly, it is preferable to correctly and speedily carry out signal transmission among chips mounted on a board and among a plurality of elements and circuit blocks within a chip.
In view of this, for example, there is a known technique in which: a timing adjustment circuit (for example, DLL circuit: Delay Locked Loop Circuit) is provided on the receiving side; a multi-phase clock is generated by delaying the input clock signal through the DLL circuit; and data is read (determined) at appropriate timing.
On the other hand, there is a known SerDes (SERializer/DESerializer) that interconverts serial data and parallel data at a high-speed interface such as a computer bus, and a DLL circuit is adopted in the SerDes as well.
The DLL circuit has a plurality of cascade-connected delay units so as to control, for example, a phase difference between a signal from a first delay unit (0 degree) and a signal from a second delay unit (360 degree) on latter stage of the first delay unit to become 0.
Then, the DLL circuit generates a plurality of signals with different phases (a multi-phase clock) using signals from the delay units between the first delay unit and the second delay unit. Note that a DLL circuit (a timing adjustment circuit) is not only adopted in SerDes but also widely adopted in a variety of electronic circuits (semiconductor integrated circuit devices).
As described above, the DLL circuit that has a plurality of cascade-connected delay units is adopted, for example, in a variety of electronic circuits such as SerDes. With such electronic circuits that adopt the DLL circuit, there is a possibility that the Phase Frequency Detector (PFD: phase detector) in the DLL circuit malfunctions, for example, upon startup by power application.
In other words, when the frequency of the input signal (an input clock signal) of the DLL circuit becomes higher, the operable range of the PFD is narrowed, thus, for example, the PFD malfunctions upon startup, which possibly makes generation of timing-adjusted output signals difficult.
In this regard, various timing adjustment circuits have been proposed.
Patent Document 1: Japanese Laid-open Patent Publication No. 2010-114873
Patent Document 2: Japanese Laid-open Patent Publication No. 2006-025131
Patent Document 3: Japanese Laid-open Patent Publication No. 2011-055482
Non-Patent Document 1: Kwon, Jae-Wook, et al., “A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface,” ESSCIRC (ESSCIRC), 2012 Proceedings of the, IEEE, September 2012